Videos that are processed by computers can be thought of as a sequence of individual still images. Each image is formed of a number of pixels, which are typically arranged in a rectangular array or matrix. The coordinate of any given pixel in the image can be determined by identifying on which horizontal line (or row) and on which vertical line (or column) within the image it is located.
Most video scaler architectures store an incoming video signal into memory in the order in which the individual pixels making up that image arrive. Thus, the whole of the uppermost row of the first image making up the video is stored, moving from the leftmost pixel to the rightmost pixel of that row. These pixels are then stored in a memory as one unit. This is repeated for the second row and so on until a10 of the pixels making up the image have been stored. This is repeated for all images making up the video.
Synchronous Dynamic Random Access Memory (SDRAM) chips are particularly suited to storing video data in this way. In SDRAM, data is stored in banks, rows and columns. One way of visualizing the arrangement of SDRAM chips is to imagine that each bank in the SDRAM memory is a large filing cabinet having a large number of rows and columns of drawers. Each drawer stores a certain amount of information and can be identified by specifying in which particular row and column of a particular filing cabinet it is located.
To avoid confusion between the rows and columns that are used as addresses into the SDRAM and those making up the images, the latter will be referred to as “horizontal lines” and “vertical lines” respectively.
In one implementation, each pixel contains twenty-four bits of information. This means that each pixel can represent one of 224=16,777,216 color values. A 48-bit wide data bus can store 48 bits, which equates to two pixels' worth of information since each pixel is twenty-four bits long. This two-pixel piece of information is often referred to as a “data word”. Double Data Rate Synchronous Dynamic Random Access Memory (DDR2 SDRAM) chips transfer two data words per clock cycle. This means that each clock cycle can store four pixels' worth of information. Thus, it takes four clock cycles to store sixteen pixels, which equates to eight data words.
FIG. 1 is a timing diagram taken from the Micron 256 Mb DDR2 datasheet, which is available from Micron Technology Inc. whose headquarters is at 8000 South, Federal Way, P.O. Box 6, Boise, ID. 83707-006, USA or via their website at http://download.micron.com/pdf/datasheets/dram/ddr2/256MbDDR2.pdf.
FIG. 1 shows sequential column access in typical DDR2 SDRAM. Sequential column access means accessing any column in a particular row in the SDRAM memory. At time T0, a READ command is issued to read column n from a particular row in a particular bank in the SDRAM memory. At a later time, T2, a further READ command is issued to read a different column b of the same bank and row. At time T3 all of the data contained in column n is returned. As can be seen in FIG. 1, there is a delay of three clock cycles, between T0 and T3, before data is returned from column n. Each of these READ commands to SDRAM results in four “data words” or “DQs” being retrieved from the relevant column of the SDRAM in two clock cycles. Thus, two clocks of data transfer retrieve four DQs, which equates to eight pixels of image data.
The second READ command is issued at T2 before the first four DQs are actually retrieved. This is referred to as “pipelining” and ensures that there are no gaps in the stream of data being accessed from one row, even if the READ commands are not issued continuously.
From time T3 onwards, two data words can be retrieved each clock cycle. This means that it takes one clock cycle to read two data words from different columns of the same row once that row is open.
FIG. 2 is a timing diagram taken from the same Micron 256 Micron 256 Mb DDR2 datasheet. FIG. 2 shows sequential row access in typical DDR2 SDRAM. FIG. 2 is different from FIG. 1 in that, instead of sequentially accessing different columns in the same row, different rows are being accessed sequentially. Sequential row access is required, for example, by 90° rotation.
A first row to be accessed, here row A, is activated by issuing an ACT (“ACTivate”) command at time T1. Then, the required column, column n, from row A is read by issuing a READ command at time T4. If it is desired to read data from a different row, whether or not is it also from the corresponding column, row A must first be “pre-charged” or closed. A PRE command is issued at time T6 and, after three clock cycles (tRP), row A is closed and another ACT command can be issued at time T9.
In contrast to sequentially reading sequential columns of one row, it takes eight clock cycles to read sequentially from different rows, since each row must be opened and closed before the next row can be read. In summary, it is eight times slower to read sequential rows as it is to read sequential columns in the same row.
In some data processing arrangements, particularly image processing arrangements, frequent sequential row access is required to process the data, which leads to long data processing times and intensive use of system resources. Random row access is required for image warping, whereby an input image is mapped into non-rectangular shapes. These and other characteristics of video-based data access have presented challenges to the processing and use of video data.